`timescale 1ns / 1ps

module spi_master_core_tb();
localparam              DATA_W = 8;

logic clk = 0;
logic rst = 0;
logic enable = 0;
logic [07:00] config_reg = 8'h03;
logic s_axi_tready;
logic s_axi_tvalid = 0;
logic [DATA_W-1:00] s_axi_tdata = 0;
logic m_axi_tready = 0;
logic m_axi_tvalid;
logic [DATA_W-1:00] m_axi_tdata;
logic sclk;
logic scs;
logic mosi;
logic miso = 0;

always
    #(1s/100_000_000/2) clk = ~clk;

initial
begin
    rst = 1; #1us;
    rst = 0; #1us;
    rst = 1;
end

initial
begin
    send_data();
end
task send_data();
    enable = 0;
    s_axi_tvalid = 0;
    #5us;
    enable = 1;
    #200ns;
    @ (posedge clk);
    s_axi_tvalid = 1;
    s_axi_tdata = 8'h34;
    @ (posedge clk);
    s_axi_tvalid = 0;
    #1us; enable = 0;

endtask

spi_master_core #
(
    .DATA_W          (  8               ),
    .SYS_FREQ        (  100_000_000     ),
    .SPI_FREQ        (  10_000_000      )
)
spi_master_coreEx01
(
    .clk             (  clk                 ),
    .rst             (  rst                 ),
    .enable          (  enable              ),
    .config_reg      (  config_reg          ),
    .s_axi_tready    (  s_axi_tready        ),
    .s_axi_tvalid    (  s_axi_tvalid        ),
    .s_axi_tdata     (  s_axi_tdata         ),
    .m_axi_tready    (  m_axi_tready        ),
    .m_axi_tvalid    (  m_axi_tvalid        ),
    .m_axi_tdata     (  m_axi_tdata         ),
    .sclk            (  sclk                ),
    .scs             (  scs                 ),
    .mosi            (  mosi                ),
    .miso            (  miso                )
);

endmodule

